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146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7284d 08h /
145 Arbitration bug fixed. igorm 7284d 08h /
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7431d 00h /
143 Bit acceptance_filter_mode was inverted. igorm 7431d 00h /
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7449d 23h /
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7449d 23h /
140 I forgot to thange one signal name. igorm 7504d 21h /
139 Signal bus_off_on added. igorm 7504d 21h /
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7544d 00h /
137 Header changed. mohor 7544d 00h /
136 Error counters changed. mohor 7544d 00h /
135 Header changed. mohor 7544d 00h /
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7651d 22h /
133 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7658d 09h /
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7658d 09h /
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7658d 09h /
130 mbist signals updated according to newest convention markom 7658d 09h /
129 Error counters changed. mohor 7674d 17h /
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7674d 18h /
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7674d 18h /

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