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Rev Log message Author Age Path
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.
igorm 7150d 22h /
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7169d 21h /
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7169d 21h /
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7172d 04h /
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.
igorm 7172d 04h /
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7172d 09h /
145 Arbitration bug fixed. igorm 7172d 09h /
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7319d 01h /
143 Bit acceptance_filter_mode was inverted. igorm 7319d 01h /
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7338d 00h /
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7338d 00h /
140 I forgot to thange one signal name. igorm 7392d 22h /
139 Signal bus_off_on added. igorm 7392d 23h /
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7432d 01h /
137 Header changed. mohor 7432d 01h /
136 Error counters changed. mohor 7432d 02h /
135 Header changed. mohor 7432d 02h /
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7539d 23h /
133 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7546d 10h /
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7546d 10h /

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