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Rev Log message Author Age Path
143 Bit acceptance_filter_mode was inverted. igorm 7295d 15h /
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7314d 14h /
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7314d 14h /
140 I forgot to thange one signal name. igorm 7369d 12h /
139 Signal bus_off_on added. igorm 7369d 12h /
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7408d 15h /
137 Header changed. mohor 7408d 15h /
136 Error counters changed. mohor 7408d 15h /
135 Header changed. mohor 7408d 15h /
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7516d 13h /

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