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URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

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Rev Log message Author Age Path
49 Added old uploaded documents to new repository. root 5469d 05h /
48 Added old uploaded documents to new repository. root 5469d 18h /
47 New directory structure. root 5469d 18h /
46 tested a new image, results are the same (i.e. works!) jwdonal 5589d 14h /
45 converted image to 72dpi jwdonal 5592d 13h /
44 converted to 72dpi jwdonal 5592d 13h /
43 updated for new top-level entity name jwdonal 5592d 13h /
42 deprecated! jwdonal 5592d 13h /
41 structural simulation models jwdonal 5592d 13h /
40 initial rev jwdonal 5592d 14h /
39 initial rev! jwdonal 5592d 14h /
38 updated for new Coregen BRAM version! jwdonal 5592d 14h /
37 new file to ignore! jwdonal 5592d 17h /
36 converted dcm_sys_to_lcd source file from verilog to VHDL so users don't have to have mixed-language simulation support. Aren't I so nice?? ;-) jwdonal 5592d 17h /
35 fixed spelling error jwdonal 5592d 17h /
34 fixed syntax jwdonal 5592d 18h /
33 added cvs edit feature jwdonal 5592d 18h /
32 initial rev jwdonal 5592d 18h /
31 moved to new location jwdonal 5592d 18h /
30 initial rev jwdonal 5592d 18h /

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