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Rev	Log message	Author	Age	Path
43	Improve instruction fetch logic	skordal	3667d 23h	/
42	Move check for stall from irq_asserted to exception_taken in EX stage	skordal	3667d 23h	/
41	Make continouous status register reads asynchronous	skordal	3667d 23h	/
40	Reduce example design clock frequency to 50 MHz - Also includes a minor change to make the address decoder/interconnect work better with burst transfers.	skordal	3667d 23h	/
39	Disable IRQs when handling exceptions	skordal	3667d 23h	/
38	Add "Hello World" test application	skordal	3668d 00h	/
37	Add macro to set the TOHOST register from C code	skordal	3668d 00h	/
36	Ensure correct read of CSR after stall	skordal	3668d 00h	/
35	Prevent jumping/branching when stalling	skordal	3668d 00h	/
34	Prevent flushing the pipeline if it is stalling	skordal	3668d 00h	/
33	Ensure correct read of CSR after stall	skordal	3668d 01h	/
32	Prevent jumping/branching when stalling	skordal	3670d 22h	/
31	Prevent flushing the pipeline if it is stalling	skordal	3670d 23h	/
30	Add testcase for a combination of instructions that fail when using cache	skordal	3673d 03h	/
29	Add reset functionality for the WB arbiter state machine	skordal	3675d 22h	/
28	Add rudimentary User's manual	skordal	3681d 22h	/
27	Prevent exceptions from being taken while stalling	skordal	3682d 00h	/
26	Prevent exceptions from being taken while stalling Jumping to an exception handler while stalling and waiting for a load/store instruction to finish can cause undefined results from the load/store instruction. This actually fixes the issue mentioned in revision r20.	skordal	3682d 03h	/
25	Add placeholder cache modules and a wishbone arbiter	skordal	3684d 07h	/
24	Remove unused STRINGIFY macros	skordal	3684d 20h	/

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[/] - Rev 43

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