OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] - Rev 57

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 Add processor datasheet skordal 3270d 19h /
56 Remove old and outdated processor manual skordal 3270d 20h /
55 Use timer_clk for the example design and SoC testbench skordal 3270d 21h /
54 Update benchmarks to work with supervisor spec v1.7 skordal 3275d 11h /
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3277d 12h /
52 Correct .data section of sw-jal test skordal 3277d 12h /
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3277d 12h /
50 Update test environment to the new supervisor ISA skordal 3289d 12h /
49 Correct spelling of "privileged" skordal 3299d 12h /
48 Create branch for upgrading to the new privileged ISA skordal 3299d 12h /
47 Tag version 0.1 of the Potato Processor skordal 3299d 20h /
46 Remove branch: cache-playground skordal 3302d 14h /
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.
skordal 3302d 14h /
44 Add instruction cache and use the WB adapter as dmem interface skordal 3302d 14h /
43 Improve instruction fetch logic skordal 3302d 14h /
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3302d 14h /
41 Make continouous status register reads asynchronous skordal 3302d 14h /
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.
skordal 3302d 14h /
39 Disable IRQs when handling exceptions skordal 3302d 14h /
38 Add "Hello World" test application skordal 3302d 15h /
37 Add macro to set the TOHOST register from C code skordal 3302d 15h /
36 Ensure correct read of CSR after stall skordal 3302d 16h /
35 Prevent jumping/branching when stalling skordal 3302d 16h /
34 Prevent flushing the pipeline if it is stalling skordal 3302d 16h /
33 Ensure correct read of CSR after stall skordal 3302d 16h /
32 Prevent jumping/branching when stalling skordal 3305d 13h /
31 Prevent flushing the pipeline if it is stalling skordal 3305d 14h /
30 Add testcase for a combination of instructions that fail when using cache skordal 3307d 18h /
29 Add reset functionality for the WB arbiter state machine skordal 3310d 14h /
28 Add rudimentary User's manual skordal 3316d 13h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.