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Rev Log message Author Age Path
66 Change UART status register to include recv buffer empty

This replaces bit 0 in the status register, previously used
for recv buffer _not_ empty, with a bit indicating if the
recv buffer _is_ empty.
skordal 3077d 18h /
65 Update platform headers and add cache control commands

Cache control is currently no-ops on Potato.
skordal 3144d 01h /
64 Add display enable support for the 7-seg module skordal 3144d 01h /
63 Upgrade makefiles for use with the upgraded toolchain skordal 3147d 01h /
62 Add a couple of missing signals to a sensitivity list skordal 3175d 02h /
61 Add 7-segment display controller to the Potato SoC skordal 3176d 06h /
60 Remove out-of-date comment skordal 3189d 22h /
59 Remove branch: "new-privileged-isa" skordal 3209d 23h /
58 Merge branch new-privileged-isa (r48-r57) into trunk

This adds support for the newly published supervisor extensions
version 1.7. In addition, a processor datasheet has been added
and the timer_clk signal has been properly connected in the
example design and the SoC testbench.
skordal 3210d 02h /
57 Add processor datasheet skordal 3210d 02h /
56 Remove old and outdated processor manual skordal 3210d 03h /
55 Use timer_clk for the example design and SoC testbench skordal 3210d 04h /
54 Update benchmarks to work with supervisor spec v1.7 skordal 3214d 18h /
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3216d 19h /
52 Correct .data section of sw-jal test skordal 3216d 19h /
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3216d 19h /
50 Update test environment to the new supervisor ISA skordal 3228d 20h /
49 Correct spelling of "privileged" skordal 3238d 19h /
48 Create branch for upgrading to the new privileged ISA skordal 3238d 19h /
47 Tag version 0.1 of the Potato Processor skordal 3239d 03h /
46 Remove branch: cache-playground skordal 3241d 21h /
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.
skordal 3241d 21h /
44 Add instruction cache and use the WB adapter as dmem interface skordal 3241d 21h /
43 Improve instruction fetch logic skordal 3241d 21h /
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3241d 21h /
41 Make continouous status register reads asynchronous skordal 3241d 21h /
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.
skordal 3241d 21h /
39 Disable IRQs when handling exceptions skordal 3241d 21h /
38 Add "Hello World" test application skordal 3241d 23h /
37 Add macro to set the TOHOST register from C code skordal 3241d 23h /

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