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Rev Log message Author Age Path
57 Add processor datasheet skordal 3246d 16h /potato/
56 Remove old and outdated processor manual skordal 3246d 17h /potato/
55 Use timer_clk for the example design and SoC testbench skordal 3246d 18h /potato/
54 Update benchmarks to work with supervisor spec v1.7 skordal 3251d 09h /potato/
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3253d 09h /potato/
52 Correct .data section of sw-jal test skordal 3253d 10h /potato/
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3253d 10h /potato/
50 Update test environment to the new supervisor ISA skordal 3265d 10h /potato/
49 Correct spelling of "privileged" skordal 3275d 09h /potato/
48 Create branch for upgrading to the new privileged ISA skordal 3275d 09h /potato/
47 Tag version 0.1 of the Potato Processor skordal 3275d 17h /potato/
46 Remove branch: cache-playground skordal 3278d 11h /potato/
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.
skordal 3278d 11h /potato/
44 Add instruction cache and use the WB adapter as dmem interface skordal 3278d 11h /potato/
43 Improve instruction fetch logic skordal 3278d 11h /potato/
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3278d 11h /potato/
41 Make continouous status register reads asynchronous skordal 3278d 12h /potato/
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.
skordal 3278d 12h /potato/
39 Disable IRQs when handling exceptions skordal 3278d 12h /potato/
38 Add "Hello World" test application skordal 3278d 13h /potato/

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