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Rev Log message Author Age Path
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3389d 21h /potato/branches/
52 Correct .data section of sw-jal test skordal 3389d 21h /potato/branches/
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3389d 21h /potato/branches/
50 Update test environment to the new supervisor ISA skordal 3401d 21h /potato/branches/
49 Correct spelling of "privileged" skordal 3411d 20h /potato/branches/
48 Create branch for upgrading to the new privileged ISA skordal 3411d 21h /potato/branches/
46 Remove branch: cache-playground skordal 3414d 22h /potato/branches/
44 Add instruction cache and use the WB adapter as dmem interface skordal 3414d 23h /potato/branches/
43 Improve instruction fetch logic skordal 3414d 23h /potato/branches/
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3414d 23h /potato/branches/
41 Make continouous status register reads asynchronous skordal 3414d 23h /potato/branches/
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.		 skordal 3414d 23h /potato/branches/
39 Disable IRQs when handling exceptions skordal 3414d 23h /potato/branches/
38 Add "Hello World" test application skordal 3415d 00h /potato/branches/
37 Add macro to set the TOHOST register from C code skordal 3415d 00h /potato/branches/
33 Ensure correct read of CSR after stall skordal 3415d 00h /potato/branches/
32 Prevent jumping/branching when stalling skordal 3417d 21h /potato/branches/
31 Prevent flushing the pipeline if it is stalling skordal 3417d 22h /potato/branches/
30 Add testcase for a combination of instructions that fail when using cache skordal 3420d 03h /potato/branches/
29 Add reset functionality for the WB arbiter state machine skordal 3422d 22h /potato/branches/

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