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Rev Log message Author Age Path
7 Little/big endian changes continued mihad 8264d 16h /
6 Little/big endian changes incorporated mihad 8264d 17h /
5 One bug fixed mihad 8266d 15h /
4 Changed defines for simulation to work without xilinx primitives mihad 8266d 16h /
3 This commit was manufactured by cvs2svn to create tag 'GATE_LEVEL_SIM_OK'. 8266d 16h /
2 Initial project import - working mihad 8266d 16h /
1 Standard project directories initialized by cvs2svn. 8266d 16h /

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