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[/] [ps2/] [tags/] [rel_13/] [rtl/] [verilog/] - Rev 51

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Rev Log message Author Age Path
51 New directory structure. root 6249d 19h /ps2/tags/rel_13/rtl/verilog/
42 This commit was manufactured by cvs2svn to create tag 'rel_13'. 8176d 16h /ps2/tags/rel_13/rtl/verilog/
29 small modifications. gorand 8196d 10h /ps2/tags/rel_13/rtl/verilog/
27 added 8-bit access to divider register. gorand 8200d 09h /ps2/tags/rel_13/rtl/verilog/
25 unit delay on registers added primozs 8234d 16h /ps2/tags/rel_13/rtl/verilog/
24 support for configurable devider added primozs 8234d 18h /ps2/tags/rel_13/rtl/verilog/
23 Added an option to use constant values instead of RAM
in the translation table.		 mihad 8328d 15h /ps2/tags/rel_13/rtl/verilog/
21 Error fixed again. simons 8329d 12h /ps2/tags/rel_13/rtl/verilog/
19 Error fixed. simons 8329d 12h /ps2/tags/rel_13/rtl/verilog/
17 resetall keyword removed. ifdef moved to a separated line. simons 8357d 11h /ps2/tags/rel_13/rtl/verilog/
15 Change the address width. simons 8362d 11h /ps2/tags/rel_13/rtl/verilog/
13 Added mouse interface and everything for its handling, cleaned up some unused code mihad 8776d 14h /ps2/tags/rel_13/rtl/verilog/
9 Added one more ps2 state machine for mouse interface mihad 8776d 15h /ps2/tags/rel_13/rtl/verilog/
7 Little/big endian changes continued mihad 8824d 11h /ps2/tags/rel_13/rtl/verilog/
6 Little/big endian changes incorporated mihad 8824d 13h /ps2/tags/rel_13/rtl/verilog/
5 One bug fixed mihad 8826d 10h /ps2/tags/rel_13/rtl/verilog/
4 Changed defines for simulation to work without xilinx primitives mihad 8826d 11h /ps2/tags/rel_13/rtl/verilog/
2 Initial project import - working mihad 8826d 12h /ps2/tags/rel_13/rtl/verilog/

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