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[/] [ps2/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 51

Rev	Log message	Author	Age	Path
51	New directory structure.	root	6157d 19h	/ps2/tags/rel_7/rtl/verilog/
28	This commit was manufactured by cvs2svn to create tag 'rel_7'.		8108d 09h	/ps2/tags/rel_7/rtl/verilog/
27	added 8-bit access to divider register.	gorand	8108d 09h	/ps2/tags/rel_7/rtl/verilog/
25	unit delay on registers added	primozs	8142d 16h	/ps2/tags/rel_7/rtl/verilog/
24	support for configurable devider added	primozs	8142d 17h	/ps2/tags/rel_7/rtl/verilog/
23	Added an option to use constant values instead of RAM in the translation table.	mihad	8236d 15h	/ps2/tags/rel_7/rtl/verilog/
21	Error fixed again.	simons	8237d 12h	/ps2/tags/rel_7/rtl/verilog/
19	Error fixed.	simons	8237d 12h	/ps2/tags/rel_7/rtl/verilog/
17	resetall keyword removed. ifdef moved to a separated line.	simons	8265d 10h	/ps2/tags/rel_7/rtl/verilog/
15	Change the address width.	simons	8270d 11h	/ps2/tags/rel_7/rtl/verilog/
13	Added mouse interface and everything for its handling, cleaned up some unused code	mihad	8684d 14h	/ps2/tags/rel_7/rtl/verilog/
9	Added one more ps2 state machine for mouse interface	mihad	8684d 14h	/ps2/tags/rel_7/rtl/verilog/
7	Little/big endian changes continued	mihad	8732d 11h	/ps2/tags/rel_7/rtl/verilog/
6	Little/big endian changes incorporated	mihad	8732d 12h	/ps2/tags/rel_7/rtl/verilog/
5	One bug fixed	mihad	8734d 09h	/ps2/tags/rel_7/rtl/verilog/
4	Changed defines for simulation to work without xilinx primitives	mihad	8734d 11h	/ps2/tags/rel_7/rtl/verilog/
2	Initial project import - working	mihad	8734d 11h	/ps2/tags/rel_7/rtl/verilog/