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Rev Log message Author Age Path
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4653d 07h /
160 Corrections derived from simulation debugging jguarin2002 4657d 23h /
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4659d 09h /
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4659d 13h /
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4660d 01h /
156 Test Bench Beta 0.1 jguarin2002 4660d 13h /
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4663d 13h /
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4666d 05h /
153 last modifications for tb_compiler.py compliance jguarin2002 4666d 05h /
152 Test bench oriented modifications jguarin2002 4670d 06h /
151 Previous Work to generate test benching jguarin2002 4729d 02h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4743d 00h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4743d 03h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4743d 03h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4745d 15h /
146 Interruption Machine jguarin2002 4753d 09h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4757d 23h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4765d 02h /
143 working on result queue sync decoding signals jguarin2002 4769d 19h /
142 Additions for the State Machine jguarin2002 4774d 17h /

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