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Rev Log message Author Age Path
167 Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync jguarin2002 4741d 23h /
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4742d 10h /
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4742d 19h /
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4743d 20h /
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4743d 22h /
162 Señales para evaluar en simulación funcional jguarin2002 4743d 22h /
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4745d 13h /
160 Corrections derived from simulation debugging jguarin2002 4750d 06h /
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4751d 15h /
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4751d 20h /
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4752d 07h /
156 Test Bench Beta 0.1 jguarin2002 4752d 19h /
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4755d 20h /
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4758d 12h /
153 last modifications for tb_compiler.py compliance jguarin2002 4758d 12h /
152 Test bench oriented modifications jguarin2002 4762d 13h /
151 Previous Work to generate test benching jguarin2002 4821d 09h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4835d 06h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4835d 09h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4835d 09h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4837d 22h /
146 Interruption Machine jguarin2002 4845d 15h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4850d 05h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4857d 09h /
143 working on result queue sync decoding signals jguarin2002 4862d 01h /
142 Additions for the State Machine jguarin2002 4866d 23h /
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4934d 01h /
140 Syncing: its awful work..... jguarin2002 4934d 07h /
139 Sync jguarin2002 4945d 21h /
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4950d 12h /

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