URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] - Rev 225

Rev	Log message	Author	Age	Path
205	Working towards a DMA oriented RayTRac	jguarin2002	4618d 12h	/
204	Working towards a DMA oriented RayTRac	jguarin2002	4618d 12h	/
203	Working towards a DMA oriented RayTRac	jguarin2002	4618d 12h	/
202	Working towards a DMA oriented RayTRac	jguarin2002	4618d 12h	/
201	files no longer needed im.vhd and fadd32long.vhd	jguarin2002	4618d 12h	/
200	raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers	jguarin2002	4618d 12h	/
199	Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work	jguarin2002	4634d 18h	/
198	Check out for the best out for the best organization so the datapath does not consume to many logic cells	jguarin2002	4634d 18h	/
197	Chnages on interconnectivity: Check out the SGDMA Sheets	jguarin2002	4644d 19h	/
196	raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues	jguarin2002	4648d 06h	/