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[/] [raytrac/] - Rev 160

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Rev Log message Author Age Path
160 Corrections derived from simulation debugging jguarin2002 5106d 12h /raytrac/
159 wrcycle\!\? No\! rwcycle.... jguarin2002 5107d 22h /raytrac/
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 5108d 02h /raytrac/
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 5108d 14h /raytrac/
156 Test Bench Beta 0.1 jguarin2002 5109d 02h /raytrac/
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 5112d 02h /raytrac/
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 5114d 18h /raytrac/
153 last modifications for tb_compiler.py compliance jguarin2002 5114d 18h /raytrac/
152 Test bench oriented modifications jguarin2002 5118d 19h /raytrac/
151 Previous Work to generate test benching jguarin2002 5177d 15h /raytrac/
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 5191d 12h /raytrac/
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 5191d 16h /raytrac/
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 5191d 16h /raytrac/
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 5194d 04h /raytrac/
146 Interruption Machine jguarin2002 5201d 22h /raytrac/
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 5206d 12h /raytrac/
144 The commented part of DPC was erased, and no longer needed. jguarin2002 5213d 15h /raytrac/
143 working on result queue sync decoding signals jguarin2002 5218d 08h /raytrac/
142 Additions for the State Machine jguarin2002 5223d 06h /raytrac/
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 5290d 07h /raytrac/
140 Syncing: its awful work..... jguarin2002 5290d 13h /raytrac/
139 Sync jguarin2002 5302d 04h /raytrac/
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 5306d 19h /raytrac/
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 5312d 19h /raytrac/
136 gogogo jguarin2002 5315d 06h /raytrac/
135 Correction on conectiveness of Datapath Control... jguarin2002 5319d 07h /raytrac/
134 State Machine, for addressing counting, internal writing & reading control and interruption generation jguarin2002 5321d 03h /raytrac/
133 Added the instructions queue jguarin2002 5322d 18h /raytrac/
132 There was amiss in the cross product datapath decoder jguarin2002 5326d 14h /raytrac/
131 Post RTL check on memblock jguarin2002 5326d 20h /raytrac/

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