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[/] [raytrac/] - Rev 210

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Rev Log message Author Age Path
210 Document advance..... towards dma oriented raytrac jguarin2002 4856d 15h /raytrac/
209 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
208 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
207 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
206 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
205 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
204 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
203 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
202 Working towards a DMA oriented RayTRac jguarin2002 4856d 15h /raytrac/
201 files no longer needed im.vhd and fadd32long.vhd jguarin2002 4856d 15h /raytrac/
200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4856d 15h /raytrac/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4872d 21h /raytrac/
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4872d 21h /raytrac/
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4882d 22h /raytrac/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4886d 09h /raytrac/
195 Document advance and changes in the design jguarin2002 4889d 06h /raytrac/
194 Work In Progress jguarin2002 4904d 12h /raytrac/
193 WIP: Main Document jguarin2002 4905d 09h /raytrac/
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4905d 21h /raytrac/
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4905d 21h /raytrac/

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