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Rev Log message Author Age Path
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4601d 06h /raytrac/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4604d 18h /raytrac/
195 Document advance and changes in the design jguarin2002 4607d 14h /raytrac/
194 Work In Progress jguarin2002 4622d 20h /raytrac/
193 WIP: Main Document jguarin2002 4623d 17h /raytrac/
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4624d 05h /raytrac/
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4624d 05h /raytrac/
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4628d 13h /raytrac/
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4628d 19h /raytrac/
188 Fitting Report jguarin2002 4630d 03h /raytrac/

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