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Rev Log message Author Age Path
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4751d 09h /raytrac/branches/
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4751d 20h /raytrac/branches/
156 Test Bench Beta 0.1 jguarin2002 4752d 08h /raytrac/branches/
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4755d 09h /raytrac/branches/
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4758d 01h /raytrac/branches/
153 last modifications for tb_compiler.py compliance jguarin2002 4758d 01h /raytrac/branches/
152 Test bench oriented modifications jguarin2002 4762d 02h /raytrac/branches/
151 Previous Work to generate test benching jguarin2002 4820d 22h /raytrac/branches/
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4834d 19h /raytrac/branches/
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4834d 22h /raytrac/branches/
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4834d 22h /raytrac/branches/
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4837d 11h /raytrac/branches/
146 Interruption Machine jguarin2002 4845d 04h /raytrac/branches/
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4849d 18h /raytrac/branches/
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4856d 22h /raytrac/branches/
143 working on result queue sync decoding signals jguarin2002 4861d 14h /raytrac/branches/
142 Additions for the State Machine jguarin2002 4866d 12h /raytrac/branches/
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4933d 14h /raytrac/branches/
140 Syncing: its awful work..... jguarin2002 4933d 20h /raytrac/branches/
139 Sync jguarin2002 4945d 10h /raytrac/branches/
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4950d 01h /raytrac/branches/
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4956d 02h /raytrac/branches/
136 gogogo jguarin2002 4958d 13h /raytrac/branches/
135 Correction on conectiveness of Datapath Control... jguarin2002 4962d 13h /raytrac/branches/
134 State Machine, for addressing counting, internal writing & reading control and interruption generation jguarin2002 4964d 09h /raytrac/branches/
133 Added the instructions queue jguarin2002 4966d 01h /raytrac/branches/
132 There was amiss in the cross product datapath decoder jguarin2002 4969d 20h /raytrac/branches/
131 Post RTL check on memblock jguarin2002 4970d 02h /raytrac/branches/
130 RayTrac Internal Memory Blocks among operands registers and Intermediate Results Fifos jguarin2002 4970d 21h /raytrac/branches/
129 Memory Block:

Identified the four circuits: External Write, External Read, Internal Write, Internal Read.		 jguarin2002 4976d 10h /raytrac/branches/

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