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[/] [raytrac/] [branches/] [fp/] - Rev 226

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226 Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia jguarin2002 4535d 07h /raytrac/branches/fp/
225 Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia jguarin2002 4535d 08h /raytrac/branches/fp/
224 Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia jguarin2002 4535d 08h /raytrac/branches/fp/
223 Reportes para NS_JULI_SDF_ASM_AP_DMA_130812_21028 jguarin2002 4542d 07h /raytrac/branches/fp/
222 documento en un 55\% jguarin2002 4542d 07h /raytrac/branches/fp/
210 Document advance..... towards dma oriented raytrac jguarin2002 4557d 03h /raytrac/branches/fp/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4573d 10h /raytrac/branches/fp/
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4583d 11h /raytrac/branches/fp/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4586d 22h /raytrac/branches/fp/
195 Document advance and changes in the design jguarin2002 4589d 19h /raytrac/branches/fp/
194 Work In Progress jguarin2002 4605d 01h /raytrac/branches/fp/
193 WIP: Main Document jguarin2002 4605d 22h /raytrac/branches/fp/
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4606d 09h /raytrac/branches/fp/
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4606d 09h /raytrac/branches/fp/
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4610d 18h /raytrac/branches/fp/
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4611d 00h /raytrac/branches/fp/
188 Fitting Report jguarin2002 4612d 07h /raytrac/branches/fp/
187 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4612d 07h /raytrac/branches/fp/
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4612d 07h /raytrac/branches/fp/
185 Well mulblock was a void inside file.... jguarin2002 4612d 21h /raytrac/branches/fp/

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