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[/] [raytrac/] [branches/] [fp/] [dpc.vhd] - Rev 179

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179 light change on code readbility for Datapath Control hardware description hdl file jguarin2002 4572d 15h /raytrac/branches/fp/dpc.vhd
176 Little changes on full result queue signals codification in order to fix a potential bug that havent beed detected at the time of the change in the code jguarin2002 4608d 04h /raytrac/branches/fp/dpc.vhd
175 Fixed a problem on the writing signal of results queue 5,6 and 7. The error was detected just right when a calculated normalized vector was about to be written in the results queues 5 6 and 7 and the write signals of those were not activated (it would remain in 0), after checking what was the problem, a codification bug was spotted. jguarin2002 4608d 04h /raytrac/branches/fp/dpc.vhd
171 After some raytrac simulation result analysis, some bugs were detected on the decodification of several datapaths. Corrections were done and tested jguarin2002 4608d 04h /raytrac/branches/fp/dpc.vhd
167 Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync jguarin2002 4610d 18h /raytrac/branches/fp/dpc.vhd
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4612d 17h /raytrac/branches/fp/dpc.vhd
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4614d 08h /raytrac/branches/fp/dpc.vhd
160 Corrections derived from simulation debugging jguarin2002 4619d 01h /raytrac/branches/fp/dpc.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4620d 15h /raytrac/branches/fp/dpc.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4627d 07h /raytrac/branches/fp/dpc.vhd
152 Test bench oriented modifications jguarin2002 4631d 08h /raytrac/branches/fp/dpc.vhd
151 Previous Work to generate test benching jguarin2002 4690d 04h /raytrac/branches/fp/dpc.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4704d 01h /raytrac/branches/fp/dpc.vhd
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4704d 04h /raytrac/branches/fp/dpc.vhd
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4704d 05h /raytrac/branches/fp/dpc.vhd
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4706d 17h /raytrac/branches/fp/dpc.vhd
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4719d 00h /raytrac/branches/fp/dpc.vhd
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4726d 04h /raytrac/branches/fp/dpc.vhd
143 working on result queue sync decoding signals jguarin2002 4730d 20h /raytrac/branches/fp/dpc.vhd
142 Additions for the State Machine jguarin2002 4735d 19h /raytrac/branches/fp/dpc.vhd

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