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[/] [raytrac/] [branches/] [fp/] [memblock.vhd] - Rev 191

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191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4630d 15h /raytrac/branches/fp/memblock.vhd
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4634d 23h /raytrac/branches/fp/memblock.vhd
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4635d 06h /raytrac/branches/fp/memblock.vhd
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4637d 15h /raytrac/branches/fp/memblock.vhd
174 Comment tweaking... its the same RTL anyway jguarin2002 4674d 02h /raytrac/branches/fp/memblock.vhd
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4680d 05h /raytrac/branches/fp/memblock.vhd
160 Corrections derived from simulation debugging jguarin2002 4684d 22h /raytrac/branches/fp/memblock.vhd
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4686d 08h /raytrac/branches/fp/memblock.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4686d 12h /raytrac/branches/fp/memblock.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4687d 00h /raytrac/branches/fp/memblock.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4693d 04h /raytrac/branches/fp/memblock.vhd
152 Test bench oriented modifications jguarin2002 4697d 05h /raytrac/branches/fp/memblock.vhd
151 Previous Work to generate test benching jguarin2002 4756d 01h /raytrac/branches/fp/memblock.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4769d 22h /raytrac/branches/fp/memblock.vhd
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4772d 14h /raytrac/branches/fp/memblock.vhd
143 working on result queue sync decoding signals jguarin2002 4796d 17h /raytrac/branches/fp/memblock.vhd
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4868d 17h /raytrac/branches/fp/memblock.vhd
140 Syncing: its awful work..... jguarin2002 4868d 23h /raytrac/branches/fp/memblock.vhd
139 Sync jguarin2002 4880d 13h /raytrac/branches/fp/memblock.vhd
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4885d 05h /raytrac/branches/fp/memblock.vhd

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