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[/] [raytrac/] [branches/] [fp_sgdma/] - Rev 200

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200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4575d 03h /raytrac/branches/fp_sgdma/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4591d 08h /raytrac/branches/fp_sgdma/
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4591d 08h /raytrac/branches/fp_sgdma/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4604d 21h /raytrac/branches/fp_sgdma/

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