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[/] [raytrac/] [branches/] [fp_sgdma/] - Rev 219

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219 RayTrac: Non tested and witouh TSE jguarin2002 4504d 10h /raytrac/branches/fp_sgdma/
218 Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : SOPC Library TCL scrip, load it into the Altera Project jguarin2002 4504d 14h /raytrac/branches/fp_sgdma/
217 Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : \n+ NIOS 2 Standard\n+ JTAG UART | UART | LCD | I2C TOUCH SCREEN\n+ DDR SDRAM | SSRAM | FLASH \n+ Avalon Memory Mapped Master Interface | Avalon Memory Mapped Slave Interface \n+ Direct Memory Access Support \n+ 18081 logic elements out of 24624 (73%) used jguarin2002 4504d 14h /raytrac/branches/fp_sgdma/
216 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4505d 05h /raytrac/branches/fp_sgdma/
215 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4505d 05h /raytrac/branches/fp_sgdma/
214 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4505d 05h /raytrac/branches/fp_sgdma/
213 Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) jguarin2002 4505d 05h /raytrac/branches/fp_sgdma/
212 DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. jguarin2002 4505d 05h /raytrac/branches/fp_sgdma/
211 Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! jguarin2002 4505d 05h /raytrac/branches/fp_sgdma/
209 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
208 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
207 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
206 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
205 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
204 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
203 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
202 Working towards a DMA oriented RayTRac jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
201 files no longer needed im.vhd and fadd32long.vhd jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4516d 18h /raytrac/branches/fp_sgdma/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4533d 00h /raytrac/branches/fp_sgdma/

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