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[/] [raytrac/] [branches/] [fp_sgdma/] - Rev 235

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Rev Log message Author Age Path
235 Tunnning delay added to q0 queue jguarin2002 4487d 03h /raytrac/branches/fp_sgdma/
234 raytrac update nothing major jguarin2002 4488d 02h /raytrac/branches/fp_sgdma/
233 raytrac sopc component updated jguarin2002 4488d 02h /raytrac/branches/fp_sgdma/
232 raytrac sopc component updated jguarin2002 4488d 02h /raytrac/branches/fp_sgdma/
231 nfetch address counter implemented in a whole register for convinience jguarin2002 4488d 03h /raytrac/branches/fp_sgdma/
230 RC 1.0 Previous rev(228), is functional and even more than this one, but is bigger and is for debugging jguarin2002 4493d 05h /raytrac/branches/fp_sgdma/
229 Total RtEngine Hardware, BUT, problems with interconnection... perhaps theres a problem with long path on ssumando5 jguarin2002 4494d 06h /raytrac/branches/fp_sgdma/
228 Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. jguarin2002 4495d 23h /raytrac/branches/fp_sgdma/
221 The change in sqrt and inv is about the path of the files with the data memory. dpc has been changed by ap_n_dpc and there was an error on RayTrac related to the load sync chain: the loading of Dot product Operation was being carried out as if it was an unary operation rather than a two operands operation jguarin2002 4505d 13h /raytrac/branches/fp_sgdma/
220 ap_n_dpc.vhd es el RTL que integra DataPathControl y ArithPipeLine jguarin2002 4505d 14h /raytrac/branches/fp_sgdma/
219 RayTrac: Non tested and witouh TSE jguarin2002 4505d 15h /raytrac/branches/fp_sgdma/
218 Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : SOPC Library TCL scrip, load it into the Altera Project jguarin2002 4505d 19h /raytrac/branches/fp_sgdma/
217 Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : \n+ NIOS 2 Standard\n+ JTAG UART | UART | LCD | I2C TOUCH SCREEN\n+ DDR SDRAM | SSRAM | FLASH \n+ Avalon Memory Mapped Master Interface | Avalon Memory Mapped Slave Interface \n+ Direct Memory Access Support \n+ 18081 logic elements out of 24624 (73%) used jguarin2002 4505d 19h /raytrac/branches/fp_sgdma/
216 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4506d 10h /raytrac/branches/fp_sgdma/
215 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4506d 10h /raytrac/branches/fp_sgdma/
214 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4506d 10h /raytrac/branches/fp_sgdma/
213 Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) jguarin2002 4506d 11h /raytrac/branches/fp_sgdma/
212 DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. jguarin2002 4506d 11h /raytrac/branches/fp_sgdma/
211 Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! jguarin2002 4506d 11h /raytrac/branches/fp_sgdma/
209 Working towards a DMA oriented RayTRac jguarin2002 4518d 00h /raytrac/branches/fp_sgdma/

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