| Rev |
Log message |
Author |
Age |
Path |
| 220 |
ap_n_dpc.vhd es el RTL que integra DataPathControl y ArithPipeLine |
jguarin2002 |
4843d 01h |
/raytrac/branches/fp_sgdma/ap_n_dpc.vhd |
| 219 |
RayTrac: Non tested and witouh TSE |
jguarin2002 |
4843d 02h |
/raytrac/branches/fp_sgdma/dpc.vhd |
| 212 |
DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. |
jguarin2002 |
4843d 22h |
/raytrac/branches/fp_sgdma/dpc.vhd |
| 204 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4855d 11h |
/raytrac/branches/fp_sgdma/dpc.vhd |
| 198 |
Check out for the best out for the best organization so the datapath does not consume to many logic cells |
jguarin2002 |
4871d 17h |
/raytrac/branches/fp_sgdma/dpc.vhd |
| 196 |
raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues |
jguarin2002 |
4885d 06h |
/raytrac/branches/fp_sgdma/dpc.vhd |
| 179 |
light change on code readbility for Datapath Control hardware description hdl file |
jguarin2002 |
4912d 13h |
/dpc.vhd |
| 176 |
Little changes on full result queue signals codification in order to fix a potential bug that havent beed detected at the time of the change in the code |
jguarin2002 |
4948d 03h |
/dpc.vhd |
| 175 |
Fixed a problem on the writing signal of results queue 5,6 and 7. The error was detected just right when a calculated normalized vector was about to be written in the results queues 5 6 and 7 and the write signals of those were not activated (it would remain in 0), after checking what was the problem, a codification bug was spotted. |
jguarin2002 |
4948d 03h |
/dpc.vhd |
| 171 |
After some raytrac simulation result analysis, some bugs were detected on the decodification of several datapaths. Corrections were done and tested |
jguarin2002 |
4948d 03h |
/dpc.vhd |
| 167 |
Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync |
jguarin2002 |
4950d 17h |
/dpc.vhd |
| 163 |
dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. |
jguarin2002 |
4952d 16h |
/dpc.vhd |
| 161 |
Changes for the sake of the firsts simulation tracking results |
jguarin2002 |
4954d 07h |
/dpc.vhd |
| 160 |
Corrections derived from simulation debugging |
jguarin2002 |
4959d 00h |
/dpc.vhd |
| 158 |
Changing std_logic_vector types to my custom far more convinients xfloat32\! |
jguarin2002 |
4960d 14h |
/dpc.vhd |
| 153 |
last modifications for tb_compiler.py compliance |
jguarin2002 |
4967d 06h |
/dpc.vhd |
| 152 |
Test bench oriented modifications |
jguarin2002 |
4971d 07h |
/dpc.vhd |
| 151 |
Previous Work to generate test benching |
jguarin2002 |
5030d 03h |
/dpc.vhd |
| 150 |
First Beta of RayTrac for a total size of 3874 lcells. Great Result\! |
jguarin2002 |
5044d 00h |
/dpc.vhd |
| 149 |
Results Queue writing signals set on a single standard logic vector rather than in individual bits |
jguarin2002 |
5044d 03h |
/dpc.vhd |
| 148 |
Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B |
jguarin2002 |
5044d 03h |
/dpc.vhd |
| 147 |
Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. |
jguarin2002 |
5046d 16h |
/dpc.vhd |
| 145 |
State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig |
jguarin2002 |
5058d 23h |
/dpc.vhd |
| 144 |
The commented part of DPC was erased, and no longer needed. |
jguarin2002 |
5066d 03h |
/dpc.vhd |
| 143 |
working on result queue sync decoding signals |
jguarin2002 |
5070d 19h |
/dpc.vhd |
| 142 |
Additions for the State Machine |
jguarin2002 |
5075d 18h |
/dpc.vhd |
| 140 |
Syncing: its awful work..... |
jguarin2002 |
5143d 01h |
/dpc.vhd |
| 139 |
Sync |
jguarin2002 |
5154d 15h |
/dpc.vhd |
| 138 |
enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes |
jguarin2002 |
5159d 06h |
/dpc.vhd |
| 136 |
gogogo |
jguarin2002 |
5167d 18h |
/dpc.vhd |
