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[/] [raytrac/] [branches/] [fp_sgdma/] [arith/] [wide/] [fmul32.vhd] - Rev 241

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241 fmul32 x 6 multipliers wide jguarin2002 4418d 21h /raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
240 last minute correction jguarin2002 4419d 01h /raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
239 wide multiplicator added to avoid optimization jguarin2002 4419d 02h /raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
238 wide multiplicator added to avoid optimization jguarin2002 4419d 02h /raytrac/branches/fp_sgdma/arith/wide/fmul32.vhd
219 RayTrac: Non tested and witouh TSE jguarin2002 4437d 19h /fmul32.vhd
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4479d 22h /fmul32.vhd
160 Corrections derived from simulation debugging jguarin2002 4553d 17h /fmul32.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4555d 07h /fmul32.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4555d 18h /fmul32.vhd
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4559d 07h /fmul32.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4561d 23h /fmul32.vhd
152 Test bench oriented modifications jguarin2002 4566d 00h /fmul32.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4638d 17h /fmul32.vhd
139 Sync jguarin2002 4749d 08h /fmul32.vhd
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4760d 00h /fmul32.vhd
121 taking out std_logic_arith from sight.... no conversions allowed jguarin2002 4805d 12h /fmul32.vhd
118 fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32 jguarin2002 4811d 23h /fmul32.vhd
96 2 floating points operands multiplication done and optimized jguarin2002 4849d 21h /fmul32.vhd
94 Optimization on the functionality of the mantissa multiplier... the results are much more precise than last revision... jguarin2002 4851d 18h /fmul32.vhd
93 New Fpbranch Directory Distribution jguarin2002 4852d 04h /fmul32.vhd

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