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[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac.vhd] - Rev 256

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256 Sign switcheroo added: a tweek to calculate the distance from observer to sphere impact point jguarin2002 4419d 22h /raytrac/branches/fp_sgdma/raytrac.vhd
249 Using a register as a 66.5 MHZ timer counter jguarin2002 4444d 17h /raytrac/branches/fp_sgdma/raytrac.vhd
248 Corrected an error on the normal jguarin2002 4452d 23h /raytrac/branches/fp_sgdma/raytrac.vhd
246 framework for conditional and accumulative operations DESCRIBED NOT IMPLEMENTED jguarin2002 4460d 03h /raytrac/branches/fp_sgdma/raytrac.vhd
243 The Registers BASE+1, BASE+2, BASE+3 are used now for debugging purposes jguarin2002 4475d 20h /raytrac/branches/fp_sgdma/raytrac.vhd
237 corrected errors in raytrac.vhd jguarin2002 4476d 22h /raytrac/branches/fp_sgdma/raytrac.vhd
234 raytrac update nothing major jguarin2002 4478d 01h /raytrac/branches/fp_sgdma/raytrac.vhd
231 nfetch address counter implemented in a whole register for convinience jguarin2002 4478d 02h /raytrac/branches/fp_sgdma/raytrac.vhd
230 RC 1.0 Previous rev(228), is functional and even more than this one, but is bigger and is for debugging jguarin2002 4483d 04h /raytrac/branches/fp_sgdma/raytrac.vhd
229 Total RtEngine Hardware, BUT, problems with interconnection... perhaps theres a problem with long path on ssumando5 jguarin2002 4484d 05h /raytrac/branches/fp_sgdma/raytrac.vhd
221 The change in sqrt and inv is about the path of the files with the data memory. dpc has been changed by ap_n_dpc and there was an error on RayTrac related to the load sync chain: the loading of Dot product Operation was being carried out as if it was an unary operation rather than a two operands operation jguarin2002 4495d 12h /raytrac/branches/fp_sgdma/raytrac.vhd
219 RayTrac: Non tested and witouh TSE jguarin2002 4495d 14h /raytrac/branches/fp_sgdma/raytrac.vhd
217 Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : \n+ NIOS 2 Standard\n+ JTAG UART | UART | LCD | I2C TOUCH SCREEN\n+ DDR SDRAM | SSRAM | FLASH \n+ Avalon Memory Mapped Master Interface | Avalon Memory Mapped Slave Interface \n+ Direct Memory Access Support \n+ 18081 logic elements out of 24624 (73%) used jguarin2002 4495d 18h /raytrac/branches/fp_sgdma/raytrac.vhd
211 Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! jguarin2002 4496d 10h /raytrac/branches/fp_sgdma/raytrac.vhd
202 Working towards a DMA oriented RayTRac jguarin2002 4507d 23h /raytrac/branches/fp_sgdma/raytrac.vhd
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4537d 17h /raytrac/branches/fp_sgdma/raytrac.vhd
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4563d 02h /raytrac.vhd
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4564d 04h /raytrac.vhd
177 Interruptions separated in diferent output ports, so we can assign them as interruptions senders.... each one of them..... jguarin2002 4588d 16h /raytrac.vhd
172 Results fifo writing signals added to the testbench jguarin2002 4600d 15h /raytrac.vhd

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