OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac.vhd] - Rev 230

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
230 RC 1.0 Previous rev(228), is functional and even more than this one, but is bigger and is for debugging jguarin2002 4451d 15h /raytrac/branches/fp_sgdma/raytrac.vhd
229 Total RtEngine Hardware, BUT, problems with interconnection... perhaps theres a problem with long path on ssumando5 jguarin2002 4452d 16h /raytrac/branches/fp_sgdma/raytrac.vhd
221 The change in sqrt and inv is about the path of the files with the data memory. dpc has been changed by ap_n_dpc and there was an error on RayTrac related to the load sync chain: the loading of Dot product Operation was being carried out as if it was an unary operation rather than a two operands operation jguarin2002 4463d 23h /raytrac/branches/fp_sgdma/raytrac.vhd
219 RayTrac: Non tested and witouh TSE jguarin2002 4464d 01h /raytrac/branches/fp_sgdma/raytrac.vhd
217 Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : \n+ NIOS 2 Standard\n+ JTAG UART | UART | LCD | I2C TOUCH SCREEN\n+ DDR SDRAM | SSRAM | FLASH \n+ Avalon Memory Mapped Master Interface | Avalon Memory Mapped Slave Interface \n+ Direct Memory Access Support \n+ 18081 logic elements out of 24624 (73%) used jguarin2002 4464d 05h /raytrac/branches/fp_sgdma/raytrac.vhd
211 Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! jguarin2002 4464d 21h /raytrac/branches/fp_sgdma/raytrac.vhd
202 Working towards a DMA oriented RayTRac jguarin2002 4476d 10h /raytrac/branches/fp_sgdma/raytrac.vhd
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4506d 04h /raytrac/branches/fp_sgdma/raytrac.vhd
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4531d 13h /raytrac.vhd
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4532d 15h /raytrac.vhd
177 Interruptions separated in diferent output ports, so we can assign them as interruptions senders.... each one of them..... jguarin2002 4557d 03h /raytrac.vhd
172 Results fifo writing signals added to the testbench jguarin2002 4569d 02h /raytrac.vhd
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4573d 15h /raytrac.vhd
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4575d 06h /raytrac.vhd
160 Corrections derived from simulation debugging jguarin2002 4579d 22h /raytrac.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4581d 12h /raytrac.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4582d 00h /raytrac.vhd
152 Test bench oriented modifications jguarin2002 4592d 06h /raytrac.vhd
151 Previous Work to generate test benching jguarin2002 4651d 02h /raytrac.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4664d 23h /raytrac.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.