| Rev |
Log message |
Author |
Age |
Path |
| 175 |
Fixed a problem on the writing signal of results queue 5,6 and 7. The error was detected just right when a calculated normalized vector was about to be written in the results queues 5 6 and 7 and the write signals of those were not activated (it would remain in 0), after checking what was the problem, a codification bug was spotted. |
jguarin2002 |
4711d 04h |
/ |
| 174 |
Comment tweaking... its the same RTL anyway |
jguarin2002 |
4711d 04h |
/ |
| 173 |
Added a procedure to support vectorblock03 type variables rendering after testbench execution |
jguarin2002 |
4711d 04h |
/ |
| 172 |
Results fifo writing signals added to the testbench |
jguarin2002 |
4711d 04h |
/ |
| 171 |
After some raytrac simulation result analysis, some bugs were detected on the decodification of several datapaths. Corrections were done and tested |
jguarin2002 |
4711d 04h |
/ |
| 170 |
Slim, suited to fit, elegant and small, optimized and well designed single precision floating point I3E754 32 bit adder |
jguarin2002 |
4711d 04h |
/ |
| 169 |
Long Stupid, version of a 32 bit floating point I3E754 Adder |
jguarin2002 |
4711d 04h |
/ |
| 168 |
Added a display function for vectorblock02 |
jguarin2002 |
4713d 18h |
/ |
| 167 |
Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync |
jguarin2002 |
4713d 18h |
/ |
| 166 |
A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way |
jguarin2002 |
4714d 05h |
/ |
| 165 |
Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) |
jguarin2002 |
4714d 14h |
/ |
| 164 |
reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again |
jguarin2002 |
4715d 15h |
/ |
| 163 |
dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. |
jguarin2002 |
4715d 17h |
/ |
| 162 |
Señales para evaluar en simulación funcional |
jguarin2002 |
4715d 17h |
/ |
| 161 |
Changes for the sake of the firsts simulation tracking results |
jguarin2002 |
4717d 08h |
/ |
| 160 |
Corrections derived from simulation debugging |
jguarin2002 |
4722d 01h |
/ |
| 159 |
wrcycle\!\? No\! rwcycle.... |
jguarin2002 |
4723d 10h |
/ |
| 158 |
Changing std_logic_vector types to my custom far more convinients xfloat32\! |
jguarin2002 |
4723d 15h |
/ |
| 157 |
For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim |
jguarin2002 |
4724d 03h |
/ |
| 156 |
Test Bench Beta 0.1 |
jguarin2002 |
4724d 15h |
/ |
| 155 |
Changes applied prior to testbenching using the script tb_compiler.py |
jguarin2002 |
4727d 15h |
/ |
| 154 |
rt_tb.vhd: This file will be used as the test bench main file |
jguarin2002 |
4730d 07h |
/ |
| 153 |
last modifications for tb_compiler.py compliance |
jguarin2002 |
4730d 07h |
/ |
| 152 |
Test bench oriented modifications |
jguarin2002 |
4734d 08h |
/ |
| 151 |
Previous Work to generate test benching |
jguarin2002 |
4793d 04h |
/ |
| 150 |
First Beta of RayTrac for a total size of 3874 lcells. Great Result\! |
jguarin2002 |
4807d 01h |
/ |
| 149 |
Results Queue writing signals set on a single standard logic vector rather than in individual bits |
jguarin2002 |
4807d 04h |
/ |
| 148 |
Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B |
jguarin2002 |
4807d 05h |
/ |
| 147 |
Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. |
jguarin2002 |
4809d 17h |
/ |
| 146 |
Interruption Machine |
jguarin2002 |
4817d 11h |
/ |
