OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] - Rev 207

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
207 Working towards a DMA oriented RayTRac jguarin2002 4584d 00h /
206 Working towards a DMA oriented RayTRac jguarin2002 4584d 00h /
205 Working towards a DMA oriented RayTRac jguarin2002 4584d 00h /
204 Working towards a DMA oriented RayTRac jguarin2002 4584d 00h /
203 Working towards a DMA oriented RayTRac jguarin2002 4584d 00h /
202 Working towards a DMA oriented RayTRac jguarin2002 4584d 00h /
201 files no longer needed im.vhd and fadd32long.vhd jguarin2002 4584d 00h /
200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4584d 00h /
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4600d 06h /
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4600d 06h /
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4610d 07h /
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4613d 18h /
195 Document advance and changes in the design jguarin2002 4616d 15h /
194 Work In Progress jguarin2002 4631d 21h /
193 WIP: Main Document jguarin2002 4632d 18h /
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4633d 06h /
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4633d 06h /
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4637d 14h /
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4637d 20h /
188 Fitting Report jguarin2002 4639d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.