| Rev |
Log message |
Author |
Age |
Path |
| 92 |
Optimizations made on ema2 and ema3: First One, ema3 and ema2 both now has a 4 pipeline, this equalization has saved lots of registers. Second One: Shifters to denormalize mantissas before addition are implemented with multipliers and inverting the bits direction in the bit vectors, resulting in a saving of resources of 332->253 LEs in ema2 (23% saving) and 608->408 LEs in ema3svn status (32% saving) |
jguarin2002 |
5409d 08h |
/ |
| 91 |
Optimizations made on ema2 and ema3: First One, ema3 and ema2 both now has a 4 pipeline, this equalization has saved lots of registers. Second One: Shifters to denormalize mantissas before addition are implemented with multipliers and inverting the bits direction in the bit vectors, resulting in a saving of resources of 332->253 LEs in ema2 (23% saving) and 608->408 LEs in ema3svn status (32% saving) |
jguarin2002 |
5409d 08h |
/ |
| 90 |
Minor corrections to ema2 zero support |
jguarin2002 |
5409d 15h |
/ |
| 89 |
floating point mult ready |
jguarin2002 |
5409d 16h |
/ |
| 88 |
Exponent Managment Addition: supports now Zero |
jguarin2002 |
5409d 17h |
/ |
| 87 |
For the sake of easyness, mmp is called now mul2 |
jguarin2002 |
5411d 17h |
/ |
| 86 |
For the sake of easyness, mmp is called now mul2 |
jguarin2002 |
5411d 17h |
/ |
| 85 |
get doesnt fit anymore... |
jguarin2002 |
5412d 09h |
/ |
| 84 |
Floating Point Adders: (ema3,add3) is an a+b+c adder and (ema2,add2) is an a+b adder. Ema's are blocks to normalize the exponents and shift the mantissas as required, add's are blocks that make the mantissa addition and normalize the result again into a 32 bit IEEE float format |
jguarin2002 |
5412d 09h |
/ |
| 83 |
Only to have it as an example of what to do to sign a mantissa |
jguarin2002 |
5412d 09h |
/ |
| 82 |
FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd |
jguarin2002 |
5415d 04h |
/ |
| 81 |
Almost There |
jguarin2002 |
5419d 02h |
/ |
| 80 |
not a revision |
jguarin2002 |
5419d 18h |
/ |
| 79 |
I can't use a 20 bits mantissa.... eliminating optimization |
jguarin2002 |
5423d 12h |
/ |
| 78 |
Metamorphosis |
jguarin2002 |
5431d 01h |
/ |
| 77 |
Now support for addition and substraction of A(7,10) component vectors |
jguarin2002 |
5431d 14h |
/ |
| 76 |
Upgrade para obtener una mantissa de 20 bits |
jguarin2002 |
5433d 12h |
/ |
| 75 |
Optimization done on matissa lenght for x**-1 and x**0.5, getting a longer mantissa of 20 bits instead one of 18 bits |
jguarin2002 |
5435d 07h |
/ |
| 74 |
On the rush, correct chip floor planning problem |
jguarin2002 |
5440d 01h |
/ |
| 73 |
Almost Ready Division and Square Root |
jguarin2002 |
5441d 06h |
/ |
| 72 |
Minor changes, is more a matter of format rather than anything... |
jguarin2002 |
5441d 18h |
/ |
| 71 |
RLshifterAlfa |
jguarin2002 |
5444d 11h |
/ |
| 70 |
RLshifterbeta++ |
jguarin2002 |
5444d 12h |
/ |
| 69 |
RLshifterbeta |
jguarin2002 |
5444d 14h |
/ |
| 68 |
On the rush cant explain what I did, but sure its about sqrtdiv |
jguarin2002 |
5445d 01h |
/ |
| 67 |
On the rush cant explain what I did, but sure its about sqrtdiv |
jguarin2002 |
5447d 03h |
/ |
| 66 |
tb.vhd moved to testbench directory |
jguarin2002 |
5448d 15h |
/ |
| 65 |
move memmaker to utils directory |
jguarin2002 |
5448d 15h |
/ |
| 64 |
Code split in directories like: sqrtdiv tb utils |
jguarin2002 |
5448d 15h |
/ |
| 63 |
square root function, from [sqrt(1.0),sqrt(2.0)). inverse function from [1/1.0, 1/2.0) |
jguarin2002 |
5448d 16h |
/ |
