OpenCores
URL https://opencores.org/ocsvn/rs232_interface/rs232_interface/trunk

Subversion Repositories rs232_interface

[/] - Rev 18

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
18 Added RX state verification for start bit process.
Added loop in the parallel interface of TB.		 akram.mashni 4732d 15h /
17 First commit of uart test bench.
WARNING: Not yet finished! Commited for back up.		 akram.mashni 5164d 22h /
16 Project's block diagram.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 5266d 07h /
15 Removed uncompressed image with big size. akram.mashni 5266d 08h /
14 Block diagram image of 2011-01-16 version.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 5266d 08h /
13 Initial commit of documentation.
Created block diagram (OpenOffice Draw format).		 akram.mashni 5266d 08h /
12 Updated news of uart.vhd commit. akram.mashni 5267d 11h /
11 Moved debouncer to a new process.
Fixed rx_clk_en generation.
Fixed start of reception condition on rx FSM.		 akram.mashni 5267d 11h /
10 Implemented asynchronous mode and RX clock regeneration.
NOT TESTED !!!		 akram.mashni 5275d 05h /
9 Updated change log. akram.mashni 5312d 20h /
8 Added Recommended Tools akram.mashni 5312d 20h /
7 Implemented PARITY (not tested!). akram.mashni 5314d 07h /
6 Fixed/improved header.
Changed SPACEs to TABs.		 akram.mashni 5315d 12h /
5 Added comments to port map. akram.mashni 5322d 16h /
4 Added "Change Log".
Added "About"		 akram.mashni 5322d 17h /
3 Added main file.
Fisrt commit.
Tested in the following conditions:
- Baud rate: 9600 bps.
- Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent)
- Main clock 50 MHz		 akram.mashni 5322d 17h /
2 Initial Commit luciorp 5379d 06h /
1 The project and the structure was created root 5407d 03h /

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.