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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 264

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Rev Log message Author Age Path
264 Final synthesis results. Gates, sdc, tcl, conf, etc. creep 5296d 04h /
263 Added the final reports from synthesis without a VCD creep 5296d 05h /
262 Final synthesis script. creep 5296d 05h /
261 Added a better clock gating scheme with enable sharing creep 5296d 08h /
260 removing useless files creep 5299d 02h /
259 sync creep 5299d 02h /
258 Fixed the input parametric testing logic, removed a pad. creep 5299d 02h /
257 Modified script for DFT creep 5321d 05h /
256 fp files creep 5321d 05h /
255 Changed the PADS verilog description to minimize violations creep 5321d 05h /
254 Fixed a latch in the design creep 5321d 05h /
253 Changed the rw_mem signal name in the hierarchy creep 5344d 05h /
252 Added a stubs file for the pads. creep 5344d 06h /
251 Added the io wrapper creep 5344d 09h /
250 Synthesis script changed creep 5344d 09h /
249 Renamed the synthesis script creep 5345d 05h /
248 Added a low power synthesis script creep 5350d 04h /
247 Added the cpu mapped verilog creep 5350d 04h /
246 Added some older files plus the first syn script creep 5351d 08h /
245 Added a few dirs for the synthesis creep 5351d 08h /

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