Subversion Repositories t6507lp

[/] - Rev 264


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Rev Log message Author Age Path
264 Final synthesis results. Gates, sdc, tcl, conf, etc. creep 5429d 17h /
263 Added the final reports from synthesis without a VCD creep 5429d 18h /
262 Final synthesis script. creep 5429d 18h /
261 Added a better clock gating scheme with enable sharing creep 5429d 20h /
260 removing useless files creep 5432d 15h /
259 sync creep 5432d 15h /
258 Fixed the input parametric testing logic, removed a pad. creep 5432d 15h /
257 Modified script for DFT creep 5454d 18h /
256 fp files creep 5454d 18h /
255 Changed the PADS verilog description to minimize violations creep 5454d 18h /
254 Fixed a latch in the design creep 5454d 18h /
253 Changed the rw_mem signal name in the hierarchy creep 5477d 18h /
252 Added a stubs file for the pads. creep 5477d 18h /
251 Added the io wrapper creep 5477d 21h /
250 Synthesis script changed creep 5477d 22h /
249 Renamed the synthesis script creep 5478d 18h /
248 Added a low power synthesis script creep 5483d 16h /
247 Added the cpu mapped verilog creep 5483d 16h /
246 Added some older files plus the first syn script creep 5484d 21h /
245 Added a few dirs for the synthesis creep 5484d 21h /

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