OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 117

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
117 Fixed the top level and connected the entire project. creep 5876d 21h /
116 Changed the module instantiation into the dot form. creep 5876d 22h /
115 Renamed the signal control. It is mem_rw now. creep 5876d 22h /
114 Created a global timescale file for the project. Added to the top module. creep 5876d 22h /
113 Timescale was unified. gabrieloshiro 5876d 22h /
112 Created a global timescale file for the project. creep 5876d 22h /
111 Performed some linting after coding was finished. creep 5877d 14h /
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5877d 15h /
109 PLA and PLP are coded and simulated. creep 5877d 18h /
108 PHA and PHP are coded and simulated. creep 5877d 18h /
107 The RTS instruction is working fine. Coded and simulated. creep 5877d 19h /
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5877d 19h /
105 The RTI instruction is working fine. Coded and simulated. creep 5877d 20h /
104 The BRK instruction is working. The reset vector was tested also. creep 5877d 21h /
103 Some early modifications to support the special stack instructions. creep 5878d 15h /
102 Some early modifications to support the special stack instructions. creep 5878d 18h /
101 Absolute indirect addressing mode is coded and simulated. creep 5878d 21h /
100 IDY WRITE TYPE instructions are coded and simulated. creep 5878d 22h /
99 Only Package.v should be used. creep 5878d 23h /
98 Updated status and some comments. creep 5878d 23h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.