URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 123

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Rev	Log message	Author	Age	Path
123	Added all the eRM files.	creep	5869d 16h	/
122	Adding alu_mon.e	creep	5869d 17h	/
121	Adding formal verification folder.	creep	5869d 17h	/
120	Added some extra commentaries.	creep	5870d 17h	/
119	removing old file.	creep	5870d 19h	/
118	The top level name was in uppercase. The correct is lowercase.	creep	5870d 21h	/
117	Fixed the top level and connected the entire project.	creep	5870d 21h	/
116	Changed the module instantiation into the dot form.	creep	5870d 21h	/
115	Renamed the signal control. It is mem_rw now.	creep	5870d 22h	/
114	Created a global timescale file for the project. Added to the top module.	creep	5870d 22h	/
113	Timescale was unified.	gabrieloshiro	5870d 22h	/
112	Created a global timescale file for the project.	creep	5870d 22h	/
111	Performed some linting after coding was finished.	creep	5871d 13h	/
110	All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage.	creep	5871d 15h	/
109	PLA and PLP are coded and simulated.	creep	5871d 17h	/
108	PHA and PHP are coded and simulated.	creep	5871d 18h	/
107	The RTS instruction is working fine. Coded and simulated.	creep	5871d 19h	/
106	First stable version. Things seems to be working. Simulation is currently at 20%.	gabrieloshiro	5871d 19h	/
105	The RTI instruction is working fine. Coded and simulated.	creep	5871d 19h	/
104	The BRK instruction is working. The reset vector was tested also.	creep	5871d 21h	/
103	Some early modifications to support the special stack instructions.	creep	5872d 15h	/
102	Some early modifications to support the special stack instructions.	creep	5872d 18h	/
101	Absolute indirect addressing mode is coded and simulated.	creep	5872d 21h	/
100	IDY WRITE TYPE instructions are coded and simulated.	creep	5872d 22h	/
99	Only Package.v should be used.	creep	5872d 22h	/
98	Updated status and some comments.	creep	5872d 22h	/
97	Removed obsolete TODO.	creep	5872d 23h	/
96	IDY READ TYPE instructions are coded and simulated. IDY WRITE TYPE instructions are coded but still requires simulation.	creep	5875d 14h	/
95	IDX addressing mode is also 100%, coded and simulated.	creep	5875d 18h	/
94	Relative addressing mode is almost 100% functional. It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.	creep	5876d 14h	/

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Subversion Repositories t6507lp

[/] - Rev 123

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