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Subversion Repositories t6507lp

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Rev Log message Author Age Path
133 Checker updated. ADD's and AND's should be working fine. creep 5804d 15h /
132 Added a .e file containing the opcodes. Other files modified as well. Chebeing written. creep 5804d 16h /
131 Added a checker for i/o comparison. creep 5807d 12h /
130 Added alu_input.e to the repository. creep 5807d 15h /
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5807d 15h /
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5807d 19h /
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5807d 20h /
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5807d 20h /
125 All files are linked to each other. RTL is still not linked through hdl_path() creep 5808d 12h /
124 All signals are mapped on the BFM and MON using the SIG_MAP. creep 5808d 14h /
123 Added all the eRM files. creep 5808d 15h /
122 Adding alu_mon.e creep 5808d 15h /
121 Adding formal verification folder. creep 5808d 15h /
120 Added some extra commentaries. creep 5809d 15h /
119 removing old file. creep 5809d 18h /
118 The top level name was in uppercase. The correct is lowercase. creep 5809d 19h /
117 Fixed the top level and connected the entire project. creep 5809d 19h /
116 Changed the module instantiation into the dot form. creep 5809d 20h /
115 Renamed the signal control. It is mem_rw now. creep 5809d 20h /
114 Created a global timescale file for the project. Added to the top module. creep 5809d 20h /

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