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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 264

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Rev Log message Author Age Path
264 Final synthesis results. Gates, sdc, tcl, conf, etc. creep 5288d 11h /t6507lp/
263 Added the final reports from synthesis without a VCD creep 5288d 11h /t6507lp/
262 Final synthesis script. creep 5288d 11h /t6507lp/
261 Added a better clock gating scheme with enable sharing creep 5288d 14h /t6507lp/
260 removing useless files creep 5291d 08h /t6507lp/
259 sync creep 5291d 08h /t6507lp/
258 Fixed the input parametric testing logic, removed a pad. creep 5291d 08h /t6507lp/
257 Modified script for DFT creep 5313d 11h /t6507lp/
256 fp files creep 5313d 11h /t6507lp/
255 Changed the PADS verilog description to minimize violations creep 5313d 11h /t6507lp/
254 Fixed a latch in the design creep 5313d 11h /t6507lp/
253 Changed the rw_mem signal name in the hierarchy creep 5336d 12h /t6507lp/
252 Added a stubs file for the pads. creep 5336d 12h /t6507lp/
251 Added the io wrapper creep 5336d 15h /t6507lp/
250 Synthesis script changed creep 5336d 15h /t6507lp/
249 Renamed the synthesis script creep 5337d 11h /t6507lp/
248 Added a low power synthesis script creep 5342d 10h /t6507lp/
247 Added the cpu mapped verilog creep 5342d 10h /t6507lp/
246 Added some older files plus the first syn script creep 5343d 14h /t6507lp/
245 Added a few dirs for the synthesis creep 5343d 15h /t6507lp/

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