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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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[/] [t6507lp/] - Rev 113

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Rev Log message Author Age Path
113 Timescale was unified. gabrieloshiro 5590d 14h /t6507lp/
112 Created a global timescale file for the project. creep 5590d 14h /t6507lp/
111 Performed some linting after coding was finished. creep 5591d 05h /t6507lp/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5591d 06h /t6507lp/
109 PLA and PLP are coded and simulated. creep 5591d 09h /t6507lp/
108 PHA and PHP are coded and simulated. creep 5591d 10h /t6507lp/
107 The RTS instruction is working fine. Coded and simulated. creep 5591d 10h /t6507lp/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5591d 11h /t6507lp/
105 The RTI instruction is working fine. Coded and simulated. creep 5591d 11h /t6507lp/
104 The BRK instruction is working. The reset vector was tested also. creep 5591d 13h /t6507lp/
103 Some early modifications to support the special stack instructions. creep 5592d 06h /t6507lp/
102 Some early modifications to support the special stack instructions. creep 5592d 09h /t6507lp/
101 Absolute indirect addressing mode is coded and simulated. creep 5592d 13h /t6507lp/
100 IDY WRITE TYPE instructions are coded and simulated. creep 5592d 14h /t6507lp/
99 Only Package.v should be used. creep 5592d 14h /t6507lp/
98 Updated status and some comments. creep 5592d 14h /t6507lp/
97 Removed obsolete TODO. creep 5592d 14h /t6507lp/
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.
creep 5595d 06h /t6507lp/
95 IDX addressing mode is also 100%, coded and simulated. creep 5595d 09h /t6507lp/
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.
creep 5596d 06h /t6507lp/

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