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Subversion Repositories t6507lp

[/] [t6507lp/] - Rev 135

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Rev Log message Author Age Path
135 Added the ASL instructions to the checker. creep 5798d 18h /t6507lp/
134 Updated the checker, it is now always one cycle behind the bfm. creep 5799d 15h /t6507lp/
133 Checker updated. ADD's and AND's should be working fine. creep 5799d 17h /t6507lp/
132 Added a .e file containing the opcodes. Other files modified as well. Chebeing written. creep 5799d 18h /t6507lp/
131 Added a checker for i/o comparison. creep 5802d 14h /t6507lp/
130 Added alu_input.e to the repository. creep 5802d 16h /t6507lp/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5802d 16h /t6507lp/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5802d 20h /t6507lp/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5802d 21h /t6507lp/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5802d 22h /t6507lp/
125 All files are linked to each other. RTL is still not linked through hdl_path() creep 5803d 13h /t6507lp/
124 All signals are mapped on the BFM and MON using the SIG_MAP. creep 5803d 16h /t6507lp/
123 Added all the eRM files. creep 5803d 16h /t6507lp/
122 Adding alu_mon.e creep 5803d 17h /t6507lp/
121 Adding formal verification folder. creep 5803d 17h /t6507lp/
120 Added some extra commentaries. creep 5804d 17h /t6507lp/
119 removing old file. creep 5804d 19h /t6507lp/
118 The top level name was in uppercase. The correct is lowercase. creep 5804d 21h /t6507lp/
117 Fixed the top level and connected the entire project. creep 5804d 21h /t6507lp/
116 Changed the module instantiation into the dot form. creep 5804d 21h /t6507lp/

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