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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] - Rev 264

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Rev Log message Author Age Path
264 Final synthesis results. Gates, sdc, tcl, conf, etc. creep 5439d 09h /t6507lp/trunk/
263 Added the final reports from synthesis without a VCD creep 5439d 10h /t6507lp/trunk/
262 Final synthesis script. creep 5439d 10h /t6507lp/trunk/
261 Added a better clock gating scheme with enable sharing creep 5439d 12h /t6507lp/trunk/
260 removing useless files creep 5442d 06h /t6507lp/trunk/
259 sync creep 5442d 06h /t6507lp/trunk/
258 Fixed the input parametric testing logic, removed a pad. creep 5442d 06h /t6507lp/trunk/
257 Modified script for DFT creep 5464d 09h /t6507lp/trunk/
256 fp files creep 5464d 09h /t6507lp/trunk/
255 Changed the PADS verilog description to minimize violations creep 5464d 09h /t6507lp/trunk/
254 Fixed a latch in the design creep 5464d 09h /t6507lp/trunk/
253 Changed the rw_mem signal name in the hierarchy creep 5487d 10h /t6507lp/trunk/
252 Added a stubs file for the pads. creep 5487d 10h /t6507lp/trunk/
251 Added the io wrapper creep 5487d 13h /t6507lp/trunk/
250 Synthesis script changed creep 5487d 13h /t6507lp/trunk/
249 Renamed the synthesis script creep 5488d 09h /t6507lp/trunk/
248 Added a low power synthesis script creep 5493d 08h /t6507lp/trunk/
247 Added the cpu mapped verilog creep 5493d 08h /t6507lp/trunk/
246 Added some older files plus the first syn script creep 5494d 13h /t6507lp/trunk/
245 Added a few dirs for the synthesis creep 5494d 13h /t6507lp/trunk/

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