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[/] [t6507lp/] [trunk/] - Rev 123

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Rev Log message Author Age Path
123 Added all the eRM files. creep 6074d 01h /t6507lp/trunk/
122 Adding alu_mon.e creep 6074d 02h /t6507lp/trunk/
121 Adding formal verification folder. creep 6074d 02h /t6507lp/trunk/
120 Added some extra commentaries. creep 6075d 02h /t6507lp/trunk/
119 removing old file. creep 6075d 05h /t6507lp/trunk/
118 The top level name was in uppercase. The correct is lowercase. creep 6075d 06h /t6507lp/trunk/
117 Fixed the top level and connected the entire project. creep 6075d 06h /t6507lp/trunk/
116 Changed the module instantiation into the dot form. creep 6075d 07h /t6507lp/trunk/
115 Renamed the signal control. It is mem_rw now. creep 6075d 07h /t6507lp/trunk/
114 Created a global timescale file for the project. Added to the top module. creep 6075d 07h /t6507lp/trunk/
113 Timescale was unified. gabrieloshiro 6075d 07h /t6507lp/trunk/
112 Created a global timescale file for the project. creep 6075d 07h /t6507lp/trunk/
111 Performed some linting after coding was finished. creep 6075d 23h /t6507lp/trunk/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 6076d 00h /t6507lp/trunk/
109 PLA and PLP are coded and simulated. creep 6076d 03h /t6507lp/trunk/
108 PHA and PHP are coded and simulated. creep 6076d 03h /t6507lp/trunk/
107 The RTS instruction is working fine. Coded and simulated. creep 6076d 04h /t6507lp/trunk/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 6076d 04h /t6507lp/trunk/
105 The RTI instruction is working fine. Coded and simulated. creep 6076d 04h /t6507lp/trunk/
104 The BRK instruction is working. The reset vector was tested also. creep 6076d 06h /t6507lp/trunk/
103 Some early modifications to support the special stack instructions. creep 6077d 00h /t6507lp/trunk/
102 Some early modifications to support the special stack instructions. creep 6077d 03h /t6507lp/trunk/
101 Absolute indirect addressing mode is coded and simulated. creep 6077d 06h /t6507lp/trunk/
100 IDY WRITE TYPE instructions are coded and simulated. creep 6077d 07h /t6507lp/trunk/
99 Only Package.v should be used. creep 6077d 08h /t6507lp/trunk/
98 Updated status and some comments. creep 6077d 08h /t6507lp/trunk/
97 Removed obsolete TODO. creep 6077d 08h /t6507lp/trunk/
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 6079d 23h /t6507lp/trunk/
95 IDX addressing mode is also 100%, coded and simulated. creep 6080d 03h /t6507lp/trunk/
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 6081d 00h /t6507lp/trunk/

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