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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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[/] [t6507lp/] [trunk/] - Rev 127

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Rev Log message Author Age Path
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5878d 01h /t6507lp/trunk/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5878d 01h /t6507lp/trunk/
125 All files are linked to each other. RTL is still not linked through hdl_path() creep 5878d 17h /t6507lp/trunk/
124 All signals are mapped on the BFM and MON using the SIG_MAP. creep 5878d 19h /t6507lp/trunk/
123 Added all the eRM files. creep 5878d 20h /t6507lp/trunk/
122 Adding alu_mon.e creep 5878d 20h /t6507lp/trunk/
121 Adding formal verification folder. creep 5878d 20h /t6507lp/trunk/
120 Added some extra commentaries. creep 5879d 20h /t6507lp/trunk/
119 removing old file. creep 5879d 23h /t6507lp/trunk/
118 The top level name was in uppercase. The correct is lowercase. creep 5880d 00h /t6507lp/trunk/
117 Fixed the top level and connected the entire project. creep 5880d 00h /t6507lp/trunk/
116 Changed the module instantiation into the dot form. creep 5880d 01h /t6507lp/trunk/
115 Renamed the signal control. It is mem_rw now. creep 5880d 01h /t6507lp/trunk/
114 Created a global timescale file for the project. Added to the top module. creep 5880d 01h /t6507lp/trunk/
113 Timescale was unified. gabrieloshiro 5880d 01h /t6507lp/trunk/
112 Created a global timescale file for the project. creep 5880d 01h /t6507lp/trunk/
111 Performed some linting after coding was finished. creep 5880d 17h /t6507lp/trunk/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5880d 18h /t6507lp/trunk/
109 PLA and PLP are coded and simulated. creep 5880d 21h /t6507lp/trunk/
108 PHA and PHP are coded and simulated. creep 5880d 22h /t6507lp/trunk/

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