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[/] [t6507lp/] [trunk/] - Rev 133

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Rev Log message Author Age Path
133 Checker updated. ADD's and AND's should be working fine. creep 5839d 07h /t6507lp/trunk/
132 Added a .e file containing the opcodes. Other files modified as well. Chebeing written. creep 5839d 08h /t6507lp/trunk/
131 Added a checker for i/o comparison. creep 5842d 04h /t6507lp/trunk/
130 Added alu_input.e to the repository. creep 5842d 06h /t6507lp/trunk/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5842d 06h /t6507lp/trunk/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5842d 10h /t6507lp/trunk/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5842d 11h /t6507lp/trunk/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5842d 12h /t6507lp/trunk/
125 All files are linked to each other. RTL is still not linked through hdl_path() creep 5843d 03h /t6507lp/trunk/
124 All signals are mapped on the BFM and MON using the SIG_MAP. creep 5843d 06h /t6507lp/trunk/
123 Added all the eRM files. creep 5843d 06h /t6507lp/trunk/
122 Adding alu_mon.e creep 5843d 07h /t6507lp/trunk/
121 Adding formal verification folder. creep 5843d 07h /t6507lp/trunk/
120 Added some extra commentaries. creep 5844d 07h /t6507lp/trunk/
119 removing old file. creep 5844d 09h /t6507lp/trunk/
118 The top level name was in uppercase. The correct is lowercase. creep 5844d 11h /t6507lp/trunk/
117 Fixed the top level and connected the entire project. creep 5844d 11h /t6507lp/trunk/
116 Changed the module instantiation into the dot form. creep 5844d 11h /t6507lp/trunk/
115 Renamed the signal control. It is mem_rw now. creep 5844d 11h /t6507lp/trunk/
114 Created a global timescale file for the project. Added to the top module. creep 5844d 12h /t6507lp/trunk/
113 Timescale was unified. gabrieloshiro 5844d 12h /t6507lp/trunk/
112 Created a global timescale file for the project. creep 5844d 12h /t6507lp/trunk/
111 Performed some linting after coding was finished. creep 5845d 03h /t6507lp/trunk/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5845d 04h /t6507lp/trunk/
109 PLA and PLP are coded and simulated. creep 5845d 07h /t6507lp/trunk/
108 PHA and PHP are coded and simulated. creep 5845d 08h /t6507lp/trunk/
107 The RTS instruction is working fine. Coded and simulated. creep 5845d 09h /t6507lp/trunk/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5845d 09h /t6507lp/trunk/
105 The RTI instruction is working fine. Coded and simulated. creep 5845d 09h /t6507lp/trunk/
104 The BRK instruction is working. The reset vector was tested also. creep 5845d 11h /t6507lp/trunk/

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