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[/] [t6507lp/] [trunk/] [rtl/] - Rev 116

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Rev Log message Author Age Path
116 Changed the module instantiation into the dot form. creep 6137d 17h /t6507lp/trunk/rtl/
115 Renamed the signal control. It is mem_rw now. creep 6137d 17h /t6507lp/trunk/rtl/
114 Created a global timescale file for the project. Added to the top module. creep 6137d 17h /t6507lp/trunk/rtl/
113 Timescale was unified. gabrieloshiro 6137d 17h /t6507lp/trunk/rtl/
112 Created a global timescale file for the project. creep 6137d 17h /t6507lp/trunk/rtl/
111 Performed some linting after coding was finished. creep 6138d 09h /t6507lp/trunk/rtl/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 6138d 10h /t6507lp/trunk/rtl/
109 PLA and PLP are coded and simulated. creep 6138d 13h /t6507lp/trunk/rtl/
108 PHA and PHP are coded and simulated. creep 6138d 13h /t6507lp/trunk/rtl/
107 The RTS instruction is working fine. Coded and simulated. creep 6138d 14h /t6507lp/trunk/rtl/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 6138d 14h /t6507lp/trunk/rtl/
105 The RTI instruction is working fine. Coded and simulated. creep 6138d 14h /t6507lp/trunk/rtl/
104 The BRK instruction is working. The reset vector was tested also. creep 6138d 16h /t6507lp/trunk/rtl/
103 Some early modifications to support the special stack instructions. creep 6139d 10h /t6507lp/trunk/rtl/
102 Some early modifications to support the special stack instructions. creep 6139d 13h /t6507lp/trunk/rtl/
101 Absolute indirect addressing mode is coded and simulated. creep 6139d 16h /t6507lp/trunk/rtl/
100 IDY WRITE TYPE instructions are coded and simulated. creep 6139d 17h /t6507lp/trunk/rtl/
99 Only Package.v should be used. creep 6139d 18h /t6507lp/trunk/rtl/
98 Updated status and some comments. creep 6139d 18h /t6507lp/trunk/rtl/
97 Removed obsolete TODO. creep 6139d 18h /t6507lp/trunk/rtl/

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