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[/] [t6507lp/] [trunk/] [rtl/] - Rev 156

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156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5863d 19h /t6507lp/trunk/rtl/
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 5864d 00h /t6507lp/trunk/rtl/
153 Added a few more instructions to the checker. Removed prints to speed up Specman. creep 5864d 17h /t6507lp/trunk/rtl/
152 Bug #24 from trac was fixed. gabrieloshiro 5864d 18h /t6507lp/trunk/rtl/
151 tah comitado! gabrieloshiro 5864d 18h /t6507lp/trunk/rtl/
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5864d 18h /t6507lp/trunk/rtl/
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5864d 19h /t6507lp/trunk/rtl/
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5864d 20h /t6507lp/trunk/rtl/
146 Fixed ticket #13: reset behavior in the FSM. creep 5865d 16h /t6507lp/trunk/rtl/
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5865d 18h /t6507lp/trunk/rtl/
144 Checker is working fine. Hunting bugs... creep 5865d 18h /t6507lp/trunk/rtl/
143 Modified the inputs so the alu resets. creep 5865d 20h /t6507lp/trunk/rtl/
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 5865d 22h /t6507lp/trunk/rtl/
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5865d 22h /t6507lp/trunk/rtl/
140 Variable names were changed according to coding guidelines. gabrieloshiro 5865d 22h /t6507lp/trunk/rtl/
139 t6507lp_package.v was renamed to avoid uppercase. creep 5865d 23h /t6507lp/trunk/rtl/
136 Some minor coding style changes. gabrieloshiro 5866d 19h /t6507lp/trunk/rtl/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5870d 18h /t6507lp/trunk/rtl/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5870d 22h /t6507lp/trunk/rtl/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5870d 23h /t6507lp/trunk/rtl/

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