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[/] [t6507lp/] [trunk/] [rtl/] - Rev 160

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Rev Log message Author Age Path
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 6097d 09h /t6507lp/trunk/rtl/
157 gabrieloshiro 6097d 09h /t6507lp/trunk/rtl/
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 6097d 11h /t6507lp/trunk/rtl/
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 6097d 16h /t6507lp/trunk/rtl/
153 Added a few more instructions to the checker. Removed prints to speed up Specman. creep 6098d 09h /t6507lp/trunk/rtl/
152 Bug #24 from trac was fixed. gabrieloshiro 6098d 09h /t6507lp/trunk/rtl/
151 tah comitado! gabrieloshiro 6098d 10h /t6507lp/trunk/rtl/
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 6098d 10h /t6507lp/trunk/rtl/
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 6098d 11h /t6507lp/trunk/rtl/
148 Reset assertion was commented. It was not working properly. gabrieloshiro 6098d 11h /t6507lp/trunk/rtl/
146 Fixed ticket #13: reset behavior in the FSM. creep 6099d 08h /t6507lp/trunk/rtl/
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 6099d 10h /t6507lp/trunk/rtl/
144 Checker is working fine. Hunting bugs... creep 6099d 10h /t6507lp/trunk/rtl/
143 Modified the inputs so the alu resets. creep 6099d 11h /t6507lp/trunk/rtl/
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 6099d 14h /t6507lp/trunk/rtl/
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 6099d 14h /t6507lp/trunk/rtl/
140 Variable names were changed according to coding guidelines. gabrieloshiro 6099d 14h /t6507lp/trunk/rtl/
139 t6507lp_package.v was renamed to avoid uppercase. creep 6099d 14h /t6507lp/trunk/rtl/
136 Some minor coding style changes. gabrieloshiro 6100d 11h /t6507lp/trunk/rtl/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 6104d 10h /t6507lp/trunk/rtl/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 6104d 14h /t6507lp/trunk/rtl/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 6104d 15h /t6507lp/trunk/rtl/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 6104d 15h /t6507lp/trunk/rtl/
120 Added some extra commentaries. creep 6106d 10h /t6507lp/trunk/rtl/
119 removing old file. creep 6106d 13h /t6507lp/trunk/rtl/
118 The top level name was in uppercase. The correct is lowercase. creep 6106d 14h /t6507lp/trunk/rtl/
117 Fixed the top level and connected the entire project. creep 6106d 14h /t6507lp/trunk/rtl/
116 Changed the module instantiation into the dot form. creep 6106d 15h /t6507lp/trunk/rtl/
115 Renamed the signal control. It is mem_rw now. creep 6106d 15h /t6507lp/trunk/rtl/
114 Created a global timescale file for the project. Added to the top module. creep 6106d 15h /t6507lp/trunk/rtl/

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