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[/] [t6507lp/] [trunk/] [rtl/] - Rev 80

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Rev Log message Author Age Path
80 Grouping some instructions that have the same behavioral. gabrieloshiro 6088d 12h /t6507lp/trunk/rtl/
79 ALU testbench added. gabrieloshiro 6088d 13h /t6507lp/trunk/rtl/
78 ZPG coded and simulated. creep 6088d 13h /t6507lp/trunk/rtl/
77 ZPG coded. Simulation is halfway. creep 6088d 13h /t6507lp/trunk/rtl/
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.		 creep 6088d 13h /t6507lp/trunk/rtl/
75 First working version! gabrieloshiro 6088d 13h /t6507lp/trunk/rtl/
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 6088d 14h /t6507lp/trunk/rtl/
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 6092d 10h /t6507lp/trunk/rtl/
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 6092d 13h /t6507lp/trunk/rtl/
67 File name change to lowercase. HAL says so! creep 6092d 15h /t6507lp/trunk/rtl/
66 File name change to lowercase. HAL says so! creep 6092d 15h /t6507lp/trunk/rtl/
65 Now the blocks are connected. gabrieloshiro 6093d 10h /t6507lp/trunk/rtl/
64 Constant were wrong. gabrieloshiro 6093d 10h /t6507lp/trunk/rtl/
63 Fixed several HAL warnings. Still plenty to do. creep 6093d 10h /t6507lp/trunk/rtl/
62 The DUT file name changed. creep 6093d 10h /t6507lp/trunk/rtl/
61 File name change to lowercase. HAL says so! creep 6093d 10h /t6507lp/trunk/rtl/
60 File name change. HAL says so! creep 6093d 10h /t6507lp/trunk/rtl/
59 I`ve fixed some latch creation. gabrieloshiro 6093d 10h /t6507lp/trunk/rtl/
58 ALU with all opcodes ready for simulation. gabrieloshiro 6093d 11h /t6507lp/trunk/rtl/
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 6093d 11h /t6507lp/trunk/rtl/

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