OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 105

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
105 The RTI instruction is working fine. Coded and simulated. creep 6142d 21h /t6507lp/trunk/rtl/verilog/
104 The BRK instruction is working. The reset vector was tested also. creep 6142d 23h /t6507lp/trunk/rtl/verilog/
103 Some early modifications to support the special stack instructions. creep 6143d 17h /t6507lp/trunk/rtl/verilog/
102 Some early modifications to support the special stack instructions. creep 6143d 20h /t6507lp/trunk/rtl/verilog/
101 Absolute indirect addressing mode is coded and simulated. creep 6143d 23h /t6507lp/trunk/rtl/verilog/
100 IDY WRITE TYPE instructions are coded and simulated. creep 6144d 00h /t6507lp/trunk/rtl/verilog/
99 Only Package.v should be used. creep 6144d 01h /t6507lp/trunk/rtl/verilog/
98 Updated status and some comments. creep 6144d 01h /t6507lp/trunk/rtl/verilog/
97 Removed obsolete TODO. creep 6144d 01h /t6507lp/trunk/rtl/verilog/
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 6146d 16h /t6507lp/trunk/rtl/verilog/
95 IDX addressing mode is also 100%, coded and simulated. creep 6146d 20h /t6507lp/trunk/rtl/verilog/
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 6147d 17h /t6507lp/trunk/rtl/verilog/
93 Opcode for BNE was wrong. creep 6147d 18h /t6507lp/trunk/rtl/verilog/
92 Absolute indexed mode working properly. All cases were simulated. creep 6147d 23h /t6507lp/trunk/rtl/verilog/
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 6147d 23h /t6507lp/trunk/rtl/verilog/
90 CMP, CPX and CPY affect carry flag (in this case it indicates a borrow) but they don't affect overflow. gabrieloshiro 6148d 00h /t6507lp/trunk/rtl/verilog/
89 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. creep 6148d 00h /t6507lp/trunk/rtl/verilog/
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 6148d 00h /t6507lp/trunk/rtl/verilog/
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 6148d 16h /t6507lp/trunk/rtl/verilog/
86 Zero page indexed mode is working fine. creep 6148d 19h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.