OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 106

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5871d 10h /t6507lp/trunk/rtl/verilog/
105 The RTI instruction is working fine. Coded and simulated. creep 5871d 10h /t6507lp/trunk/rtl/verilog/
104 The BRK instruction is working. The reset vector was tested also. creep 5871d 12h /t6507lp/trunk/rtl/verilog/
103 Some early modifications to support the special stack instructions. creep 5872d 05h /t6507lp/trunk/rtl/verilog/
102 Some early modifications to support the special stack instructions. creep 5872d 08h /t6507lp/trunk/rtl/verilog/
101 Absolute indirect addressing mode is coded and simulated. creep 5872d 12h /t6507lp/trunk/rtl/verilog/
100 IDY WRITE TYPE instructions are coded and simulated. creep 5872d 13h /t6507lp/trunk/rtl/verilog/
99 Only Package.v should be used. creep 5872d 13h /t6507lp/trunk/rtl/verilog/
98 Updated status and some comments. creep 5872d 13h /t6507lp/trunk/rtl/verilog/
97 Removed obsolete TODO. creep 5872d 13h /t6507lp/trunk/rtl/verilog/
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.
creep 5875d 05h /t6507lp/trunk/rtl/verilog/
95 IDX addressing mode is also 100%, coded and simulated. creep 5875d 08h /t6507lp/trunk/rtl/verilog/
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.
creep 5876d 05h /t6507lp/trunk/rtl/verilog/
93 Opcode for BNE was wrong. creep 5876d 07h /t6507lp/trunk/rtl/verilog/
92 Absolute indexed mode working properly. All cases were simulated. creep 5876d 11h /t6507lp/trunk/rtl/verilog/
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 5876d 11h /t6507lp/trunk/rtl/verilog/
90 CMP, CPX and CPY affect carry flag (in this case it indicates a borrow) but they don't affect overflow. gabrieloshiro 5876d 12h /t6507lp/trunk/rtl/verilog/
89 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. creep 5876d 12h /t6507lp/trunk/rtl/verilog/
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5876d 13h /t6507lp/trunk/rtl/verilog/
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5877d 04h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.